参数资料
型号: IDT7024L17PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/22页
文件大小: 0K
描述: IC SRAM 64KBIT 17NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K(4K x 16)
速度: 17ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7024L17PF8
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (2,4,5) (M/ S = V IH )
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t DW
VALID
t DH
ADDR "B"
t APS
(1)
MATCH
BUSY "B"
DATA OUT "B"
NOTES:
t BAA
t WDD
t DDD (3)
t BDA
t BDD
VALID
2740 drw 13
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE).
2. CE L = CE R = V IL .
3. OE = V IL for the reading port.
4. If M/ S = V IL (slave) then BUSY is an input BUSY "A" = V IL and BUSY "B" = don't care, for this example.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY
t WP
R/ W "A"
t WB (3)
BUSY "B"
t WH
(1)
R/ W "B"
(2)
,
2740 drw 14
NOTES:
1. t WH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" Blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB is only for the 'Slave' Version.
14
6.42
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