参数资料
型号: IDT7024L30J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 20/22页
文件大小: 0K
描述: IC SRAM 64KBIT 30NS 84PLCC
标准包装: 200
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K(4K x 16)
速度: 30ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.21x29.21)
包装: 带卷 (TR)
其它名称: 7024L30J8
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
2K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
L PORT
SEMAPHORE
REQUEST FLIP FLOP
Military, Industrial and Commercial Temperature Ranges
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D 0
D
Q
Q
D
D 0
WRITE
SEMAPHORE
READ
Figure 4. IDT7024 Semaphore Logic
20
6.42
WRITE
SEMAPHORE
READ
2740 drw 20
,
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