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| 型号： | IDT7024L55PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/22页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 64KBIT 55NS 100TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 64K（4K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7024L55PF8 |
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
t HZ (7)
OE
t AW
CE or SEM
UB or LB
(9)
(9)
t AS (6)
t WP (2)
t WR
(3)
R/ W
t WZ
(7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
CE or SEM
DATA IN
2740 drw 09
Timing Waveform of Write Cycle No. 2, CE , UB , LB Controlled Timing (1,5)
t WC
ADDRESS
t AW
(9)
UB or LB
(9)
R/ W
t AS (6)
t EW (2)
t DW
t WR (3)
t DH
DATA IN
2740 drw 10
NOTES:
1. R/ W or CE or UB & LB = V IH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a UB or LB = V IL and a CE = V IL and a R/ W = V IL for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W ) going HIGH = V IL to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE , R/ W , UB , or LB .
7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load
(Figure 2).
8. If OE = V IL during R/ W controlled write cycle, the write pulse width must be the larger of t WP for (t WZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t WP .
9. To access RAM, CE = V IL , UB or LB = V IL , and SEM = V IH . To access Semaphore, CE = V IH or UB & LB = V IH , and SEM = V IL . t EW must be
met for either condition.
11
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