参数资料
型号: IDT7025L17J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/22页
文件大小: 0K
描述: IC SRAM 128KBIT 17NS 84PLCC
标准包装: 200
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K(8K x 16)
速度: 17ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.21x29.21)
包装: 带卷 (TR)
其它名称: 7025L17J8
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
IDT7025S/L
True Dual-Ported memory cells which allow simultaneous
High-speed access
Low-power operation
Separate upper-byte and lower-byte control for multiplexed
Features
reads of the same memory location
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
– IDT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
bus compatibility
Functional Block Diagram
R/ W L
UB L
LB L
CE L
OE L
I/O 8L -I/O 15L
I/O
IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/ S = H for BUSY output flag on Master
M/ S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/ W R
UB R
LB R
CE R
OE R
I/O 8R -I/O 15R
I/O
BUSY R
I/O 0L -I/O 7L
(1,2)
BUSY L
Control
Control
I/O 0R -I/O 7R
(1,2)
A 12L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 12R
A 0R
13
ARBITRATION
13
INT L
SEM L
(2)
CE L
OE L
R/ W L
INTERRUPT
SEMAPHORE
LOGIC
M/ S
CE R
OE R
R/ W R
SEM R
INT R (2)
2683 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
?2012 Integrated Device Technology, Inc.
1
JULY 2012
DSC 2683/11
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