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| 型号： | IDT7025L17PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 17NS 100TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 17ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7025L17PF8 |
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Truth Table II — Address BUSY
Arbitration
Military, Industrial and Commercial Temperature Ranges
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A 0L -A 12L
A 0R -A 12R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
NOTES:
2683 tbl 17
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSY x outputs on the IDT7025
are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table III — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
D 0 - D 15 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2683 tbl 18
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.
2. There are eight semaphore flags written to via I/O 0 and read from all I/0's. These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH , SEM = V IL , to access the semaphores. Refer to the Semaphore Read/Write Truth Table.
Functional Description
The IDT7025 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7025 has an automatic power down feature controlled
by CE . The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected ( CE = V IH ).
When a port is enabled, access to the entire memory array is permitted.
I nterrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(HEX), where a write is defined as the CE R = R/ W R = V IL per Truth Table
I. The left port clears the interrupt by an address location 1FFE access
when CE L = OE L = V IL , R/ W L is a "don't care". Likewise, the right port
interrupt flag (INT R ) is asserted when the left port writes to memory location
1FFF (HEX) and to clear the interrupt flag ( INT R ), the right port must access
the memory location 1FFF , The message (16 bits) at 1FFE or 1FFF is
user-defined, since it is an addressable SRAM location. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used as
mail boxes, but as part of the random access memory. Refer to Truth Table
I for the interrupt operation.
( INT L ) is asserted when the right port writes to memory location 1FFE
18
6.42
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