参数资料
型号: IDT7025L30J
厂商: IDT, Integrated Device Technology Inc
文件页数: 15/22页
文件大小: 0K
描述: IC SRAM 128KBIT 30NS 84PLCC
标准包装: 15
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K(8K x 16)
速度: 30ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.21x29.21)
包装: 管件
其它名称: 7025L30J
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Port-to-Port Read and BUSY (2,4,5) (M/ S = V IH )
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t DW
VALID
t DH
ADDR "B"
t APS
(1)
MATCH
BUSY "B"
t BAA
t WDD
t BDA
t BDD
DATA OUT "B"
NOTES:
t DDD
(3)
VALID
2683 drw 13
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (slave).
2. CE L = CE R = V IL .
3. OE = V IL for the reading port.
4. If M/ S = V IL (SLAVE), then BUSY is an input. Therefore in this example BUSY "A" = V IH and BUSY "B" input is shown.
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".
Timing Waveform of Write with BUSY
t WP
R/ W "A"
BUSY "B"
t WB (3)
R/ W "B"
(2)
t WH
(1)
NOTES:
1. t WH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on port "B" Blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB is only for the 'Slave' Version .
15
6.42
2683 drw 14
.
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