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参数资料
| 型号： | IDT7025L55J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 84PLCC |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC（29.21x29.21） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7025L55J8 |
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range (6)
7025X15
Com'l Ony
7025X17
Com'l Only
7025X20
Com'l, Ind
& Military
7025X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
t APS
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time (2)
____
____
____
____
5
15
15
15
15
____
____
____
____
____
5
17
17
17
17
____
____
____
____
____
5
20
20
20
17
____
____
____
____
____
5
20
20
20
17
____
ns
ns
ns
ns
ns
Write Hold After BUSY
t BDD
t WH
BUSY Disable to Valid Data
(5)
(3)
____
12
18
____
____
13
18
____
____
15
30
____
____
17
30
____
ns
ns
BUSY TIMING (M/ S = V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
12
____
____
0
13
____
____
0
15
____
____
0
17
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
30
____
30
____
45
____
50
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
25
____
35
____
35
ns
2683 tbl 14a
7025X35
Com'l &
Military
7025X55
Com'l, Ind
& Military
7025X70
Military Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/ S = V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
____
____
____
____
20
20
20
20
____
____
____
____
45
40
40
35
____
____
____
____
45
40
40
35
ns
ns
ns
ns
BUSY Disable to Valid Data
t APS
t BDD
t WH
Arbitration Priority Set-up Time
(3)
Write Hold After BUSY (5)
(2)
5
____
25
____
35
____
5
____
25
____
40
____
5
____
25
____
45
____
ns
ns
ns
BUSY TIMING (M/ S = V IL )
t WB
t WH
BUSY Input to Write (4)
Write Hold After BUSY (5)
0
25
____
____
0
25
____
____
0
25
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
t DDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay (1)
____
____
60
45
____
____
80
65
____
____
95
80
ns
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/ S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0ns, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part number indicates power rating (S or L).
14
6.42
2683 tbl 14b
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