参数资料
型号: IDT70261S55PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/19页
文件大小: 0K
描述: IC SRAM 256KBIT 55NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K(16K x 16)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 70261S55PF8
Features
HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM WITH INTERRUPT
IDT70261S/L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial 20/25ns (max.)
Low-power operation
– IDT70261S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT70261L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/ S = H for BUSY output flag on Master,
M/ S = L for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (-40 O C to +85 O C) is available
for selected speeds
Functional Block Diagram
R/ W L
UB L
LB L
CE L
OE L
R/ W R
UB R
LB R
CE R
OE R
BUSY R
I/O 8L -I/O 15L
I/O 0L -I/O 7L
(1,2)
BUSY L
I/O
Control
I/O
Control
I/O 8R -I/O 15R
I/O 0R -I/O 7R
(1,2)
A 13L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 13R
A 0R
14
14
SEM L
CE L
OE L
R/ W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE R
OE R
R/ W R
SEM R
INT L
(2)
M/ S
INT R (2)
3039 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
JANUARY 2009
1
?2009 Integrated Device Technology, Inc.
DSC 3039/10
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