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参数资料
| 型号： | IDT707288L20G |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS |
| 中文描述： | 高速64K的× 16 BANK-SWITC哈布莱双端口SRAM与外部银行选择 |
| 文件页数： | 4/6页 |
| 文件大小： | 65K |
| 代理商： | IDT707288L20G |
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
6.29
4
NOTES:
1. Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second
16Kx16 memory spaces, Bank 2 to the third 16Kx16 memory spaces,
and Bank 3 to the fourth 16Kx16 memory spaces. 'LEFT' indicates the
bank is assigned to the left port; 'RIGHT' indicates the bank is assigned
to the right port.
2. The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs
are not tri-statable. When changing the bank select inputs (changing
the bank assignments), the device must be write-disabled (
CE
and/or
R/
W
set to V
IH
).
3. 'H' = V
IH
, 'L' = V
IL
, 'X' = Don't Care.
ASSIGNING THE BANKS VIA THE EXTERNAL BANK
SELECTS
There are four bank select pins available on the IDT707288,
and each of these pins is associated with a specific bank within
the memory array. The pins are user-controlled inputs:
access to a specific bank is assigned to a particular port by
setting the input to the appropriate level. The process of
assigning the banks is detailed in Truth Table I. Once a bank
is assigned to a port, the owning port has full access to read
and write within that bank. The opposite port is unable to
access that bank until the user reassigns the port. Access by
TRUTH TABLE I –
MEMORY BANK ASSIGNMENT
(
CE
AND/OR R/
W
= V
IH
)
(2,3)
BANK AND
DIRECTION
(1)
BANK 0 LEFT
BANK 1 LEFT
BANK 2 LEFT
BANK 3 LEFT
BANK 0 RIGHT
BANK 1 RIGHT
BANK 2 RIGHT
BANK 3 RIGHT
BKSEL0
H
X
X
X
L
X
X
X
BKSEL1
X
H
X
X
X
L
X
X
BKSEL2
X
X
H
X
X
X
L
X
BKSEL3
X
X
X
H
X
X
X
L
3592 tbl 02
MAILBOX INTERRUPTS AND INTERRUPT CONTROL
REGISTERS
If the user chooses to use the mailbox interrupt function,
four mailbox locations are assigned to each port. These
mailbox locations are external to the memory array. The
mailboxes are accessed by taking
MBSEL
Low while holding
CE
High.
The mailboxes are 16 bits wide: the message is user-
defined since these are addressable SRAM locations. An
interrupt is generated to the opposite port upon writing to the
upper byte of any mailbox location. A port can read the
message it has just written in order to verify it: this read will
not alter the status of the interrupt sent to the opposite port.
The interrupted port can clear the interrupt by reading the
upper byte of the applicable mailbox. This read will not alter
the contents of the mailbox. The use of mailboxes to generate
interrupts to the opposite port and the reading of mailboxes to
clear interrupts is detailed in Truth Table II.
If desired, any of the mailbox interrupts can be indepen-
dently masked via software. Masking of the interrupt sources
is done in the Mask Register. The masks are individual and
independent: a port can mask any combination of interrupt
sources with no effect on the other sources. Each port can
modify only its own Mask Register. The use of this register is
detailed in Truth Table II.
Two registers are provided to permit interpretation of
interrupts: these are the Interrupt Cause Register and the
Interrupt Status Register. The Interrupt Cause Register gives
the user a snapshot of what has caused the interrupt to be
generated - a specific semaphore granted to that port or a
specific mailbox written to by the opposite port. The informa-
tion in this register provides post-mask signals: interrupt
sources that have been masked will not be updated. The
Interrupt Status Register gives the user the status of all bits
that could potentially cause an interrupt regardless of whether
they have been masked. The use of the Interrupt Cause
Register and the Interrupt Status Register is detailed in Truth
Table II.
a port to a bank which it does not control will have no effect if
written, and if read unknown values on D
0
-D
15
will be returned.
Each port can be assigned as many banks within the array as
needed, up to and including all four banks.
The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs are not tri-statable. When changing the bank
select inputs (changing the bank assignments), the device
must be write-disabled (
CE
and/or R/
W
set to V
IH
).
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