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参数资料
| 型号： | IDT707288S20PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| 中文描述： | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM, TQFP-100 |
| 文件页数： | 1/6页 |
| 文件大小： | 65K |
| 代理商： | IDT707288S20PF |
HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
FEATURES:
64K x 16 Bank-Switchable Dual-Ported
SRAM Architecture
- Four independent 16K x 16 banks
- 1 Megabit of memory on chip
Fast asynchronous address-to-data access time: 20ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address &
data busses
Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without
external logic
UB
and
LB
are available for bus matching to x8 or x16
busses; also support very fast banking
TTL-compatible, single 5V (
±
10%) power supply
Available in a 100-pin Thin Quad Plastic Flatpack (TQFP)
and a 108-pin ceramic Pin Grid Array (PGA)
ADVANCED
IDT707288S/L
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1996
1996 Integrated Device Technology, Inc.
DSC-3592/-
1
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.29
DESCRIPTION:
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-
Switchable Dual-Ported SRAM organized into four indepen-
dent 16K x 16 banks. The device has two independent ports
with separate controls, addresses, and I/O pins for each port,
allowing each port to asynchronously access any 16K x 16
memory block not already accessed by the other port. Ac-
cesses by the ports into specific banks are controlled via bank
select pin inputs under the user's control. Mailboxes are
provided to allow inter-processor communications. Interrupts
are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables
(
CE
0
and CE
1
) permits the on-chip circuitry of each port to
enter a very low standby power mode and allows fast depth
expansion.
The IDT707288 offers a maximum address-to-data access
time as fast as 20ns, while typically operating on only 900mW
of power, and is available in a 100-pin Thin Quad Plastic
Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
MUX
R/
L
0L
CE
1L
L
L
L
I/O
8L-15L
I/O
0L-7L
A
13L
A
0L(1)
A
5L(1)
A
0L(1)
L
/
L
L
L
L
R/
MAILBOX
INTERRUPT
LOGIC
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
MUX
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
R/
R
0R
CE
1R
R
R
R
I/O
8R-15R
I/O
0R-7R
A
13R
A
0R(1)
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
A
5R(1)
A
0R(1)
R
/
R
R
R/
R
R
3592 drw 01
R
R
L
L
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
BA
1R
BA
0R
BA
1L
BA
0L
FUNCTIONAL BLOCK DIAGRAM
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins
serve as mailbox address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT707288S25G | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| IDT707288S25PF | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| IDT707288L20G | HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS |
| IDT707288L20PF | HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS |
| IDT707288L25G | HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS |
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