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参数资料
| 型号： | IDT707288S25G |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| 中文描述： | 高速64K的× 16 BANK-SWITC哈布莱双端口SRAM与外部银行选择 |
| 文件页数： | 2/6页 |
| 文件大小： | 65K |
| 代理商： | IDT707288S25G |
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
6.29
2
PIN NAMES
A
0
- A
13
(1,6)
BA
0
- BA
1
(1)
MBSEL
(1)
BKSEL
(2)
R/
W
(1)
OE
(1)
CE0
, CE1
(1)
UB
,
LB
(1)
I/O
0
– I/O
15
(1)
INT
(1)
V
CC
(4)
GND
(5)
NOTES:
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the
assignment of that bank between the two ports. Refer to Table I for more
details.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as bank address or memory address inputs. When
MBSEL
= V
IL
, the pins serve as mailbox address inputs.
Address Inputs
Bank Address Inputs
Mailbox Access Control Gate
Bank Select Inputs
Read/Write Enable
Output Enable
Chip Enables
I/O Byte Enables
Bidirectional Data Input/Output
Interrupt Flag (Output)
(3)
+5V Power
Ground
FUNCTIONALITY:
The IDT707288 is a high-speed asynchronous 64K x 16
Bank-Switchable Dual-Ported SRAM, organized in four 16K x
16 banks. The two ports are permitted independent, simulta-
neous access into separate banks within the shared array.
There are four user-controlled Bank Select input pins , and
each of these pins is associated with a specific bank within the
memory array. Access to a specific bank is gained by placing
the associated Bank Select pin in the appropriate state: V
IH
assigns the bank to the left port, and V
IL
assigns the bank to
the right port (See Truth Table I). Once a bank is assigned to
a particular port, the port has full access to read and write
within that bank. Each port can be assigned as many banks
within the array as needed, up to and including all four banks.
The IDT707288 provides mailboxes to allow inter-proces-
sor communications. Each port has four 16-bit mailbox
registers available to which it can write and read and which the
opposite port can read only. These mailboxes are external to
the common SRAM array, and are accessed by setting
MBSEL
= V
IL
while setting
CE
= V
IH
. Each mailbox has an
associated interrupt: a port can generate an interrupt to the
opposite port by writing to the upper byte of any one of its four
16-bit mailboxes. The interrupted port can clear the interrupt
by reading the upper byte. This read will not alter the contents
of the mailbox.
If desired, any source of interrupt can be independently
masked via software. Two registers are provided to permit
interpretation of interrupts: the Interrupt Cause Register and
the Interrupt Status Register. The Interrupt Cause Register
gives the user a snapshot of what has caused the interrupt to
be generated - the specific mailbox written to. The information
in this register provides post-mask signals: Interrupt sources
that have been masked will not be updated. The Interrupt
Status Register gives the user the status of all bits that could
potentially cause an interrupt regardless of whether they have
been masked. Truth Table II gives a detailed explanation of
the use of these registers.
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
NOTES:
PIN CONFIGURATIONS
(1,2)
3592 tbl 01
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT707288
PN100-1
100-PIN
TQFP
TOP VIEW(3)
GND
GND
I/O
15R
OE
R
R/
W
R
MBSEL
R
GND
CE
1R
CE
0R
BKSEL
3
LB
R
NC
A
9R
A
10R
A
11R
A
13R
A
8R
A
7R
A
6R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
UB
R
3592 drw 02
I/O
15L
I/O
14L
GND
GND
OE
L
R/
W
L
MBSEL
L
CE
1L
CE
0L
Vcc
BKSEL
0
A
11L
A
13L
A
10L
NC
A
9L
A
8L
A
7L
A
6L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
UB
L
LB
L
I
5
I
4
I
3
I
2
I
0
I
0
G
I
2
I
4
I
5
I
6
I
7
L
I
3
I
1
I
7
I
8
I
9
I
8
I
9
I
6
A
4
A
5
A
4
A
3
A
0
A
1
I
R
I
L
B
1
A
3
A
5
G
V
I
L
V
G
N
B
0
B
1
A
1
A
2
B
2
G
N
A
0
A
1
B
0
B
1
A
1
A
2
相关PDF资料 |
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