参数资料
型号: IDT709279S15PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 5/18页
文件大小: 0K
描述: IC SRAM 512KBIT 15NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 512K (32K x 16)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 709279S15PF8
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (V CC = 5.0V ± 10%)
709279/69S/L
Input Leakage Current
Symbol
|I LI |
|I LO |
V OL
V OH
Parameter
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V CC = 5.5V, V IN = 0V to V CC
CE 0 = V IH or CE 1 = V IL , V OUT = 0V to V CC
I OL = +4mA
I OH = -4mA
Min.
___
___
___
2.4
Max.
10
10
0.4
___
Unit
μA
μA
V
V
3243 tbl 08
NOTE:
1. At V CC < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (6) (V CC = 5V ± 10%)
709279/69X6
Com'l Only
709279/69X7
Com'l Only
709279/69X9
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ. (4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
I CC
Dynamic Operating
Current
(Both Ports Active)
CE L and CE R = V IL
Outputs Disabled
f = f MAX (1)
COM'L
IND
S
L
S
270
270
____
585
525
____
250
250
____
490
440
____
210
210
____
390
350
____
mA
L
____
____
____
____
____
____
I SB1
Standby Current
(Both Ports - TTL
CE L = CE R = V IH
f = f MAX (1)
COM'L
S
L
80
80
205
175
65
65
170
145
50
50
135
115
mA
Level Inputs)
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I SB2
I SB3
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE "A" = V IL and
CE "B" = V IH (3)
Active Port Outputs
Disabled, f=f MAX (1)
Both Ports CE R and
CE L > V CC - 0.2V
V IN > V CC - 0.2V or
V IN < 0.2V, f = 0 (2)
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
180
180
____
____
1.0
0.2
____
405
360
____
____
15
5
____
160
160
____
____
1.0
0.2
____
340
295
____
____
15
5
____
140
140
____
____
1.0
0.2
____
270
240
____
____
15
5
____
mA
mA
L
____
____
____
____
____
____
I SB4
Full Standby Current
(One Port -
CE "A" < 0.2V and
CE "B" > V CC - 0.2V (5)
COM'L
S
L
170
170
395
340
150
150
330
290
130
130
245
225
mA
CMOS Level Inputs)
V IN > V CC - 0.2V or
V IN < 0.2V, Active Port Outputs
Disabled, f = f MAX (1)
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
NOTES:
3243 tbl 09
1. At f = f MAX , address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC , using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V CC = 5V, TA = 25°C for Typ, and are not production tested. I CC DC (f=0) = 150mA (Typ).
5. CE X = V IL means CE 0X = V IL and CE 1X = V IH
CE X = V IH means CE 0X = V IH or CE 1X = V IL
CE X < 0.2V means CE 0X < 0.2V and CE 1X > V CC - 0.2V
CE X > V CC - 0.2V means CE 0X > V CC - 0.2V or CE 1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
5
6.42
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