参数资料
型号: IDT709349L7BF
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/16页
文件大小: 0K
描述: IC SRAM 72KBIT 7NS 100FBGA
标准包装: 60
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 72K(4K x 18)
速度: 7ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LFBGA
供应商设备封装: 100-CABGA(10x10)
包装: 托盘
其它名称: 709349L7BF
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Industrial and Commercial Temperature Ranges
Left Port
CE 0L , CE 1L
R/ W L
OE L
Right Port
CE 0R , CE 1R
R/ W R
OE R
Names
Chip Enables (3)
Read/Write Enable
Output Enable
A 0L - A 12L
(1)
A 0R - A 12R
(1)
Address
I/O 0L - I/O 17L
CLK L
UB L
LB L
I/O 0R - I/O 17R
CLK R
UB R
LB R
Data Input/Output
Clock
Upper Byte Select (2)
Lower Byte Select (2)
ADS L
CNTEN L
CNTRST L
FT /PIPE L
ADS R
CNTEN R
CNTRST R
FT /PIPE R
V CC
GND
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (5V)
Ground (0V)
NOTES:
1. A 12 is a NC for IDT709349.
2. LB and UB are single buffered regardless of state of FT /PIPE.
3. CE o and CE 1 are single buffered when FT /PIPE = V IL ,
CE o and CE 1 are double buffered when FT /PIPE = V IH ,
i.e. the signals take two cycles to deselect.
5633 tbl 01
Truth Table I—Read/Write and Enable Control (1,2,3)
OE
X
X
X
X
X
X
L
L
L
H
CLK
X
CE 0 (5)
H
X
L
L
L
L
L
L
L
L
CE 1 (5)
X
L
H
H
H
H
H
H
H
H
UB (4)
X
X
H
L
H
L
L
H
L
X
LB (4)
X
X
H
H
L
L
H
L
L
X
R/ W
X
X
X
L
L
L
H
H
H
X
Upper Byte
I/O 9-17
High-Z
High-Z
High-Z
DATA IN
High-Z
DATA IN
DATA OUT
High-Z
DATA OUT
High-Z
Lower B yte
I/O 0-8
High-Z
High-Z
High-Z
High-Z
DATA IN
DATA IN
High-Z
DATA OUT
DATA OUT
High-Z
Mode
Deselected —Power Down
Deselected —Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
NOTES:
5633 tbl 02
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. ADS , CNTEN , CNTRST = X.
3. OE is an asynchronous input signa
4. LB and UB are single buffered regardless of state of FT /PIPE.
5. CE o and CE 1 are single buffered when FT /PIPE = V IL . CE o and CE 1 are double buffered when FT /PIPE = V IH , i.e. the signals take two cycles to deselect.
6.42
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