参数资料
型号: IDT70P258L55BYGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/23页
文件大小: 0K
描述: IC SRAM 128KBIT 55NS 100BGA
标准包装: 90
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K(8K x 16)
速度: 55ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-VFBGA
供应商设备封装: 100-CABGA(6x6)
包装: 托盘
其它名称: 70P258L55BYGI
800-1375
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Timing Waveform of Read with BUSY (2,4,5) (M/ S = V IH )
t WC
Industrial Temperature Range
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t DW
VALID
t DH
ADDR "B"
t APS
(1)
MATCH
t BAA
BUSY "B"
t WDD
DATA OUT "B"
t DDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (slave).
2. CE L = CE R = V IL .
3. OE = V IL for the reading port.
4. If M/ S = V SS (slave), BUSY is an input. Then for this example BUSY "A" = V IH and BUSY "B" input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
Timing Waveform of Slave Write (M/ S = V IL )
t WP
R/ W "A"
t WB (3)
BUSY "B"
t WH (1)
R/ W "B"
(2)
5675 drw 11 ,
NOTES :
1. t WH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB is only for the “slave” version.
14
6.42
t BDA
t BDD
VALID
5675 drw 10
,
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