参数资料
型号: IDT70T3319S133DDI
厂商: IDT, Integrated Device Technology Inc
文件页数: 18/27页
文件大小: 0K
描述: IC SRAM 4MBIT 133MHZ 144TQFP
产品变化通告: Product Discontinuation 20/Aug/2008
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 4.5M(256K x 18)
速度: 133MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP 裸露焊盘
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
其它名称: 70T3319S133DDI
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs) (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
An
INTERNAL (3)
ADDRESS
An (7)
An + 1
An + 2
An + 3
An + 4
t SAD t HAD
ADS
t SCN t HC
CNTEN
t SD t HD
N
DATA IN
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
WRITE
EXTERNAL
ADDRESS
WRITE WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5652 drw 17
,
Timing Waveform of Counter Repeat (2)
t CYC2
t CH2
t CL2
CLK
t SA t HA
(4)
ADDRESS
An
An + 1
An + 2
INTERNAL (3)
ADDRESS
Ax
LAST ADS LOAD
LAST ADS +1
An
An + 1
t SW t HW
R/ W
ADS
CNTEN
t SRPT t HRPT
t SAD t HAD
t SCN t HCN
REPEAT
DATA IN
(5)
t SD
t HD
D 0
DATA OUT
Q LAST
Q LAST+1
Qn
NOTES:
(6)
EXECUTE WRITE
REPEAT LAST ADS
ADDRESS
1. CE 0 , UB , LB , and R/ W = V IL ; CE 1 and REPEAT = V IH .
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
READ
ADDRESS n
READ
ADDRESS n+1
5652 drw 18
,
2. CE 0 , UB , LB = V IL ; CE 1 = V IH .
3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .
4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
18
6.42
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