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参数资料
| 型号： | IDT70T3539MS166BC8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 21/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 166MHZ 256BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 18M（512K x 36） |
| 速度： | 166MHz |
| 接口： | 并联 |
| 电源电压： | 2.4 V ~ 2.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-CABGA（17x17） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70T3539MS166BC8 |
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Functional Description
The IDT70T3539M provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE 0 or a LOW on CE 1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3539Ms for depth
expansion configurations. Two cycles are required with CE 0 LOW and
CE 1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag ( INT L ) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CE R = R/ W R = V IL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CE L = V IL and R/ W L = V IH . Likewise, the
right port interrupt flag ( INT R ) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag ( INT R ), the right port must read the memory location 7FFFF. The
message (36 bits) at 7FFFE or 7FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 7FFFE and 7FFFF are not used as mail boxes, but as part of
the random access memory. Refer to Truth Table III for the interrupt
operation.
Collision Detection
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
Industrial and Commercial Temperature Ranges
same starting address on both ports and one or both ports writing
during each access (i.e., imposes a long string of collisions on
contiguous clock cycles), the alert flag will be asserted and cleared
every other cycle. Please refer to the Collision Detection timing
waveform on Page 19.
Collision detection on the IDT70T3539M represents a significant
advance in functionality over current sync multi-ports, which have no
such capability. In addition to this functionality the IDT70T3539M
sustains the key features of bandwidth and flexibility. The collision
detection function is very useful in the case of bursting data, or a string
of accesses made to sequential addresses, in that it indicates a
problem within the burst, giving the user the option of either repeating
the burst or continuing to watch the alert flag to see whether the
number of collisions increases above an acceptable threshold value.
Offering this function on chip also allows users to reduce their need for
arbitration circuits, typically done in CPLD’s or FPGA’s. This reduces
board space and design complexity, and gives the user more flexibility
in developing a solution.
Sleep Mode
TThe IDT70T3539M is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is asynchronous
and active high. During normal operation, the ZZ pin is pulled low. When
ZZ is pulled high, the port will enter sleep mode where it will meet lowest
possible power conditions. The sleep mode timing diagram shows the
modes of operation: Normal Operation, No Read/Write Allowed and Sleep
Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = V IH ) and three cycles after de-asserting ZZ (ZZx = V IL ), the device
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/ W x = V IH )when chip enable is asserted, and the chip
enable must be valid for one full cycle before a read will result in the output
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (I ZZ ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
not be a valid write from either port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag ( COL X ) is asserted on the 2nd or 3rd rising clock
edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision Detection Timing Table on Page
19. During that next cycle, the internal arbitration is engaged in
resetting the alert flag (this avoids a specific requirement on the part of
the user to reset the alert flag). If two collisions occur on subsequent
clock cycles, the second collision may not generate the appropriate
alert flag. A third collision will generate the alert flag as appropriate. In
the event that a user initiates a burst access on both ports with the
21
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参数描述 |
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| IDT70T3539MS166BCG | 功能描述:IC SRAM 18MBIT 166MHZ 256BGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70T3589S133BC | 功能描述:IC SRAM 2MBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70T3589S133BC8 | 功能描述:IC SRAM 2MBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70T3589S133BCI | 功能描述:IC SRAM 2MBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70T3589S133BCI8 | 功能描述:IC SRAM 2MBIT 133MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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