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参数资料
| 型号： | IDT70T3799MS166BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/25页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 9MBIT 166MHZ 324BGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 9M（128K x 72） |
| 速度： | 166MHz |
| 接口： | 并联 |
| 电源电压： | 2.4 V ~ 2.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 324-BGA |
| 供应商设备封装： | 324-PBGA（19x19） |
| 包装： | 托盘 |
| 其它名称： | 70T3799MS166BBG |
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read
CLK "A"
(1,2,4)
R/ W "A
"
t SW
t SA
t HW
t HA
ADDRESS "A"
DATA IN"A"
MATCH
t SD
t HD
VALID
NO
MATCH
t CO (3)
CLK "B"
t CD2
R/ W "B"
t SW
t SA
t HW
t HA
ADDRESS "B"
DATA OUT"B"
MATCH
NO
MATCH
VALID
NOTES:
t DC
5687 drw 09
,
1. CE 0 , BE n , and ADS = V IL ; CE 1 , CNTEN , and REPEAT = V IH .
2. OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t CO + 2 t CYC2 + t CD2 ). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t CO + t CYC2 + t CD2 ).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
CLK "A"
t SW t HW
R/ W "A"
(1,2,4)
t SA
t HA
ADDRESS "A"
MATCH
t SD
t HD
NO
MATCH
DATA IN
"A"
VALID
t CO
(3)
CLK "B"
t CD1
R/ W "B"
t SW
t SA
t HW
t HA
ADDRESS "B"
MATCH
NO
MATCH
t CD1
DATA OUT "B"
NOTES:
t DC
VALID
t DC
VALID
5687 drw 10
,
1. CE 0 , BE n, and ADS = V IL ; CE 1 , CNTEN , and REPEAT = V IH .
2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
t CO + t CYC + t CD1 ). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be t CO + t CD1 ).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
13
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