参数资料
型号: IDT70T631S8BF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 19/27页
文件大小: 0K
描述: IC SRAM 4MBIT 8NS 208FBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 4.5M(256K x 18)
速度: 8ns
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 带卷 (TR)
其它名称: 70T631S8BF8
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Waveform of Interrupt Timing (1)
t WC
Industrial and Commercial Temperature Ranges
ADDR "A"
CE "A"(3)
R/ W "A"
t AS (4)
(2)
INTERRUPT SET ADDRESS
t WR (5)
t INS
(4)
INT "B"
.
5670 drw 18
t RC
ADDR "B"
INTERRUPT CLEAR ADDRESS
(4)
t AS
(2)
CE "B"(3)
OE "B"
t INR (4)
INT "B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CE X = V IL means CE 0X = V IL and CE 1X = V IH . CE X = V IH means CE 0X = V IH and/or CE 1X = V IL .
4. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
5. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
Truth Table III — Interrupt Flag (1,4)
Left Port
Right Port
5670 drw 19
.
H
L
H
R/ W L
L
X
X
X
CE L
L
X
X
L
OE L
X
X
X
L
A 18L -A 0L (5)
7FFFF
X
X
7FFFE
INT L
X
X
(3)
(2)
R/ W R
X
X
L
X
CE R
X
L
L
X
OE R
X
L
X
X
A 18R -A 0R (5)
X
7FFFF
7FFFE
X
INT R
L (2)
(3)
X
X
Function
Set Right INT R Flag
Reset Right INT R Flag
Set Left INT L Flag
Reset Left INT L Flag
NOTES:
1. Assumes BUSY L = BUSY R =V IH . CE X = L means CE 0X = V IL and CE 1X = V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
4. INT L and INT R must be initialized at power-up.
5. A 18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.
19
5670 tbl 17
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