参数资料
型号: IDT70V05L25PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 18/22页
文件大小: 0K
描述: IC SRAM 64KBIT 25NS 64TQFP
标准包装: 45
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 25ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 托盘
其它名称: 70V05L25PF
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Truth Table III — Interrupt Flag (1)
L e f t P o r t
R i g h t P o r t
Industrial and Commercial Temperature Ranges
H
L
R/ W L
L
X
X
X
C E L
L
X
X
L
O E L
X
X
X
L
A 1 2 L - A 0 L
1 F F F
X
X
1 F F E
I N T L
X
X
( 3 )
H ( 2 )
R / W R
X
X
L
X
C E R
X
L
L
X
O E R
X
L
X
X
A 1 2 R - A 0 R
X
1 F F F
1 F F E
X
I N T R
L ( 2 )
( 3 )
X
X
F u n c t i o n
S e t R i g h t I N T R F l a g
R e s e t R i g h t I N T R F l a g
S e t L e f t I N T L F l a g
R e s e t L e f t I N T L F l a g
NOTES:
1. Assumes BUSY L = BUSY R = V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
Truth Table IV — Address BUSY
Arbitration
2 9 4 1 t b l 1 5
I n p u t s
O u t p u t s
C E L
X
H
X
L
C E R
X
X
H
L
A 1 2 L - A 0 L
A 1 2 R - A 0 R
N O M A T C H
M A T C H
M A T C H
M A T C H
B U S Y L ( 1 )
H
H
H
( 2 )
B U S Y R ( 1 )
H
H
H
( 2 )
F u n c t i o n
N o r m a l
N o r m a l
N o r m a l
W r i t e I n h i b i t ( 3 )
NOTES:
2 9 4 1 t b l 1 6
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY X outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSY X input internally inhibits writes.
2. V IL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V IH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY R outputs are driving low regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
F u n c t i o n s
N o A c t i o n
L e f t P o r t W r i t e s " 0 " t o S e m a p h o r e
R i g h t P o r t W r i t e s " 0 " t o S e m a p h o r e
L e f t P o r t W r i t e s " 1 " t o S e m a p h o r e
L e f t P o r t W r i t e s " 0 " t o S e m a p h o r e
R i g h t P o r t W r i t e s " 1 " t o S e m a p h o r e
L e f t P o r t W r i t e s " 1 " t o S e m a p h o r e
R i g h t P o r t W r i t e s " 0 " t o S e m a p h o r e
R i g h t P o r t W r i t e s " 1 " t o S e m a p h o r e
L e f t P o r t W r i t e s " 0 " t o S e m a p h o r e
L e f t P o r t W r i t e s " 1 " t o S e m a p h o r e
NOTES:
D 0 - D 7 L e f t
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 7 R i g h t
1
1
1
0
0
1
1
0
1
1
1
S t a t u s
S e m a p h o r e f r e e
L e f t p o r t h a s s e m a p h o r e t o k e n
N o c h a n g e . R i g h t s i d e h a s n o w r i t e a c c e s s t o s e m a p h o r e
R i g h t p o r t o b t a i n s s e m a p h o r e t o k e n
N o c h a n g e . L e f t p o r t h a s n o w r i t e a c c e s s t o s e m a p h o r e
L e f t p o r t o b t a i n s s e m a p h o r e t o k e n
S e m a p h o r e f r e e
R i g h t p o r t h a s s e m a p h o r e t o k e n
S e m a p h o r e f r e e
L e f t p o r t h a s s e m a p h o r e t o k e n
S e m a p h o r e f r e e
2 9 4 1 t b l 1 7
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O 0 -I/O 7 ). These eight semaphores are addressed by A 0 -A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
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