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参数资料
| 型号： | IDT70V3379S4PRF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 576KBIT 4NS 128TQFP |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 576K（32K x 18） |
| 速度： | 4ns |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70V3379S4PRF8 |
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Truth Table II—Address Counter Control (1,2)
Industrial and Commercial Temperature Ranges
Previous
Addr
L
L
Address
X
An
An
X
Address
X
X
Ap
Ap
Used
0
An
Ap
Ap + 1
CLK (6)
↑
↑
↑
↑
ADS
X
(4)
H
H
CNTEN
X
X
H
L (5)
CNTRST
(4)
H
H
H
I/O (3)
D I/O (0)
D I/O (n)
D I/O (p)
D I/O (p+1)
MODE
Counter Reset to Address 0
External Address Used
External Address Blocked —Counter disabled (Ap reused)
Counter Enabled —Internal Address generation
NOTES:
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/ W , CE 0 , CE 1 , BE n and OE .
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE 0 , CE 1 and BE n
5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE 0 , CE 1 , BE n.
4833 tbl 03
Recommended Operating
Temperature and Supply Voltage (1)
Recommended DC Operating
Conditions with V DDQ at 2.5V
Ambient
Symbol
Parameter
Min.
Typ.
Max.
Unit
Grade
Commercial
Industrial
Temperature
0 O C to +70 O C
-40 O C to +85 O C
GND
0V
0V
V DD
3.3V + 150mV
3.3V + 150mV
V DD
V DDQ
V SS
Core Supply Voltage
I/O Supply Voltage (3)
Ground
3.15
2.375
0
3.3
2.5
0
3.45
2.625
0
V
V
V
4833 tbl 04
NOTES:
1. This is the parameter T A . This is the "instant on" case tempereature.
V IH
V IH
V IL
Input High Voltage (3)
(Address & Control Inputs)
Input High Voltage - I/O (3)
Input Low Voltage
1.7
1.7
-0.3 (1)
____
____
____
V DDQ + 125mV (2)
V DDQ + 125mV (2)
0.7
V
V
V
NOTES:
1. V IL > -1.5V for pulse width less than 10 ns.
4833 tb l 05a
Absolute Maximum Ratings (1)
2. V TERM must not exceed V DDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
Symbol
V TERM (2)
Rating
Terminal Voltage
Commercial
& Industrial
-0.5 to +4.6
Unit
V
OPT pin for that port must be set to V IL (0V), and V DDQX for that port must be
supplied as indicated above.
T BIAS
with Respect to
GND
Temperature
-55 to +125
o
C
Recommended DC Operating
Conditions with V DDQ at 3.3V
Under Bias
Symbol
Parameter
Min.
Typ.
Max.
Unit
T STG
Storage
-65 to +150
o
C
V DD
Core Supply Voltage
3.15
3.3
3.45
V
Temperature
V DDQ
I/O Supply Voltage
(3)
3.15
3.3
3.45
V
I OUT
DC Output Current
50
mA
V SS
Ground
0
0
0
V
4833 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
V IH
Input High Voltage
(Address & Control Inputs) (3)
2.0
____
V DDQ + 150mV
(2)
V
-0.3
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
V IH
V IL
Input High Voltage - I/O (3)
Input Low Voltage
2.0
(1)
____
____
V DDQ + 150mV (2)
0.8
V
V
maximum rating conditions for extended periods may affect reliability.
2. V TERM must not exceed V DD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of V TERM > V DD + 150mV.
NOTES:
1. V IL > -1.5V for pulse width less than 10 ns.
4833 tbl 05b
2. V TERM must not exceed V DDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V IH (3.3V), and V DDQX for that port must be
supplied as indicated above.
6.42
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