参数资料
型号: IDT70V35L20PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/25页
文件大小: 0K
描述: IC SRAM 144KBIT 20NS 100TQFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 144K(8K x 18)
速度: 20ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 70V35L20PF
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
IDT70V35/34S/L
IDT70V25/24S/L
Features
Separate upper-byte and lower-byte control for multiplexed
True Dual-Ported memory cells which allow simultaneous
bus compatibility
reads of the same memory location
IDT70V35/34 (IDT70V25/24) easily expands data bus width
High-speed access
IDT70V35/34
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25/24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
M/ S = V IH for BUSY output flag on Master
M/ S = V IL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
Low-power operation
between ports
– IDT70V35/34S
– IDT70V35/34L
Fully asynchronous operation from either port
Active: 430mW (typ.) Active: 415mW (typ.)
Standby: 3.3mW (typ.) Standby: 660 μ W (typ.)
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
– IDT70V25/24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V25/24L
Active: 380mW (typ.)
Standby: 660 μ W (typ.)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/ W L
UB L
LB L
CE L
OE L
I/O 9L -I/O 17L (5)
I/O
I/O
R/ W R
UB R
LB R
CE R
OE R
I/O 9R -I/O 17R (5)
,
BUSY L
I/O 0L -I/O 8L (4)
(2,3)
Control
Control
I/O 0R -I/O 8R (4)
BUSY R (2,3)
A 12L (1)
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 12R (1)
A 0R
13
13
CE L
OE L
R/ W L
SEM L
INT L (3)
NOTES:
1. A 12 is a NC for IDT70V34 and for IDT70V24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O 0 x - I/O 7 x for IDT70V25/24.
5. I/O 8 x - I/O 15 x for IDT70V25/24.
?2008 Integrated Device Technology, Inc.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/ S
1
CE R
OE R
R/ W R
SEM R
INT R (3)
5624 drw 01
OCTOBER 2008
DSC-5624/7
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