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| 型号： | IDT70V9279S9PRF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 512KBIT 9NS 128TQFP |
| 标准包装： | 6 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 512K (32K x 16) |
| 速度： | 9ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 70V9279S9PRF |
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read (1,2,3,5)
CLK "A"
R/ W "A"
t SW
t SA
t HW
t HA
ADDRESS "A"
DATA IN "A"
MATCH
t SD
t HD
VALID
t CCS
(4)
NO
MATCH
CLK "B"
t CD1
R/ W "B"
t SW
t SA
t HW
t HA
ADDRESS "B"
MATCH
NO
MATCH
DATA OUT "B"
t DC
t CWDD
(4)
VALID
t CD1
t DC
VALID
3743 drw 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE 0 , UB , LB , and ADS = V IL ; CE 1 , CNTEN , and CNTRST = V IH .
3. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.
4. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for t CWDD .
If t CCS > maximum specified, then data from right port READ is not valid until t CCS + t CD1 . t CWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform of Left Port Write to Pipelined Right Port Read (1,2,4)
CLK "A"
R/ W "A
"
t SW
t SA
t HW
t HA
ADDRESS "A"
DATA IN"A"
MATCH
t SD
t HD
VALID
NO
MATCH
t CO (3)
CLK "B"
t CD2
R/ W "B"
t SW
t SA
t HW
t HA
ADDRESS "B"
DATA OUT"B"
MATCH
NO
MATCH
VALID
NOTES:
t DC
3743 drw 10
,
1. CE 0 , BE n , and ADS = V IL ; CE 1 , CNTEN , and REPEAT = V IH .
2. OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t CO + 2 t CYC2 + t CD2 ). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t CO + t CYC2 + t CD2 ).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
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相关代理商/技术参数 |
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| IDT70V9279S9PRF8 | 功能描述:IC SRAM 512KBIT 9NS 128TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V9279S9PRFI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 512KBIT 9NS 128TQFP |
| IDT70V9279S9PRFI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 512KBIT 9NS 128TQFP |
| IDT70V9289L12PRF | 功能描述:IC SRAM 1MBIT 12NS 128TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V9289L12PRF8 | 功能描述:IC SRAM 1MBIT 12NS 128TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
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