参数资料
型号: IDT7130SA55J
厂商: IDT, Integrated Device Technology Inc
文件页数: 16/21页
文件大小: 0K
描述: IC SRAM 8KBIT 55NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 8K (1K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
其它名称: 7130SA55J
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing (1)
ADDR
'A' AND 'B'
CE 'B'
CE 'A'
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
BUSY 'A'
2689 drw 14
Timing Waveform by BUSY Arbitration Controlled
by Address Match Timing (1)
t RC OR t WC
ADDR 'A'
ADDR 'B'
t APS
(2)
ADDRESSES MATCH
t BAA
ADDRESSES DO NOT MATCH
t BDA
BUSY 'B'
2689 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (2)
7130X20 (1)
7140X20 (1)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
20
20
0
0
____
____
____
____
25
25
0
0
____
____
____
____
25
25
ns
ns
ns
ns
NOTES:
1. PLCC, TQFP and STQFP package only.
2. 'X' in part numbers indicates power rating (SA or LA).
16
2689 tbl 12a
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