参数资料
型号: IDT71321SA35TF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/17页
文件大小: 0K
描述: IC SRAM 16KBIT 35NS 64STQFP
标准包装: 1,250
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 带卷 (TR)
其它名称: 71321SA35TF8
Features
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71321/421LA
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
Two INT flags for port-to-port communications
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE L
CE L
R/ W L
OE R
CE R
R/ W R
I/O 0L - I/O 7L
I/O
I/O
I/O 0R -I/O 7R
BUSY L
BUSY R
(1,2)
Control
Control
(1,2)
A 10L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 10R
A 0R
11
11
INT L
INT R
(2)
CE L
OE L
R/ W L
ARBITRATION
and
INTERRUPT
LOGIC
CE R
OE R
R/ W R
(2)
2691 drw 01
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270 ? .
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270 ? .
OCTOBER 2008
1
?2008 Integrated Device Technology, Inc.
DSC-2691/13
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