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参数资料
| 型号： | IDT7132LA25JI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 16KBIT 25NS 52PLCC |
| 标准包装： | 24 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 16K (2K x 8) |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 管件 |
| 其它名称： | 7132LA25JI |
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range (5,6)
7132X20 (2)
7142X20 (2)
Com'l Only
7132X25 (2)
7142X25 (2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
t AS
t WP
t WR
t DW
Write Cycle Time (3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width (4)
Write Recovery Time
Data Valid to End-of-Write
20
15
15
0
15
0
10
____
____
____
____
____
____
____
25
20
20
0
15
0
12
____
____
____
____
____
____
____
35
30
30
0
25
0
15
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1)
____
10
____
10
____
15
ns
Write Enable to Output in High-Z
t DH
t WZ
Data Hold Time
(1)
0
____
____
10
0
____
____
10
0
____
____
15
ns
ns
t OW
Output Active from End-of-Write
(1)
0
____
0
____
0
____
ns
2692 tbl 09
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
Write Pulse Width
t WC
t EW
t AW
t AS
t WP
t WR
t DW
t HZ
t DH
t WZ
Write Cycle Time (3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
(4)
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1)
Data Hold Time
Write Enable to Output in High-Z (1)
55
40
40
0
30
0
20
____
0
____
____
____
____
____
____
____
____
25
____
30
100
90
90
0
55
0
40
____
0
____
____
____
____
____
____
____
____
40
____
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t OW
Output Active from End-of-Write
(1)
0
____
0
____
ns
NOTES:
2692 tbl 10
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, t WC = t BAA + t WP , since R/W = V IL must occur after t BAA .
4. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the
bus for the required t DW . If OE is High during a R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
9
6.42
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| IDT7132LA25JI8 | 功能描述:IC SRAM 16KBIT 25NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
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