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参数资料
| 型号： | IDT7132LA55PDGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 16KBIT 55NS 48DIP |
| 标准包装： | 7 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 16K (2K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 48-PDIP |
| 包装： | 管件 |
| 其它名称： | 7132LA55PDGI |
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (7,8)
7132X20 (1)
7142X20 (1)
Com'l Only
7132X25 (2)
7142X25 (2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY Timing (For Master IDT7132 Only)
t BAA
t BDA
t BAC
t BDC
t WDD
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay (2)
____
____
____
____
____
20
20
20
20
50
____
____
____
____
____
20
20
20
20
50
____
____
____
____
____
20
20
20
20
60
ns
ns
ns
ns
ns
t WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t DDD
t APS
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time (3)
(2)
____
5
35
____
____
5
35
____
____
5
35
____
ns
ns
t BDD
BUSY Disable to Valid Data
(4)
____
25
____
35
____
35
ns
BUSY Timing (For Slave IDT7142 Only)
t WB
Write to BUSY Input (5)
0
____
0
____
0
____
ns
t WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t WDD
t DDD
Write Pulse to Data Delay (2)
Write Data Valid to Read Data Delay (2)
____
____
40
30
____
____
50
35
____
____
60
35
ns
ns
2692 tbl 11a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY Timing (For Master IDT7132 Only)
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
____
____
____
____
30
30
30
30
____
____
____
____
50
50
50
50
ns
ns
ns
ns
t WDD
Write Pulse to Data Delay
(2)
____
80
____
120
ns
Write Hold After BUSY
t WH
t DDD
(6)
Write Data Valid to Read Data Delay (2)
20
____
____
55
20
____
____
100
ns
ns
t APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
ns
t BDD
BUSY Disable to Valid Data
(4)
____
50
____
65
ns
BUSY Timing (For Slave IDT7142 Only)
t WB
t WH
Write to BUSY Input (5)
Write Hold After BUSY (6)
0
20
____
____
0
20
____
____
ns
ns
t WDD
Write Pulse to Data Delay
(2)
____
80
____
120
ns
t DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100
ns
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
11
6.42
2692 tbl 11b
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相关代理商/技术参数 |
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