参数资料
型号: IDT71342LA25J
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/14页
文件大小: 0K
描述: IC SRAM 32KBIT 25NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 32K (4K x 8)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
其它名称: 71342LA25J
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side (1,2,4)
t RC
ADDRESS
t OH
t AA
or t SAA
t OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
2721 drw 07
Timing Waveform of Read Cycle No. 2, Either Side (1,3)
t SOP
t ACE
CE or SEM
(5)
t SOP
t AOE (4)
t HZ
(2)
OE
DATA OUT
t LZ
(1)
VALID DATA
(4)
t HZ
(2)
I CC
t PU
t LZ
(1)
t PD
CURRENT
I SB
50%
50%
2721 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is de-asserted first, OE or CE .
3. R/ W = V IH and OE = V IL , unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; t AOE , t ACE , or t AA
5. To access SRAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . t AA is for SRAM Address Access and t SAA is for Semaphore Address Access.
Timing Waveform of Write with Port-to-Port Read (2,3)
t WC
ADDR "A"
R/ W "A"
(1)
MATCH
t WP
t DW
t DH
DATA IN "A"
ADDR "B"
VALID
MATCH
t WDD
DATA OUT "B"
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CE L = CE R = V IL. CE "B" = V IL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
7
6.42
t DDD
VALID
2721 drw 09
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