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参数资料
| 型号： | IDT7134SA35J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 35NS 52PLCC |
| 标准包装： | 400 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K (4K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7134SA35J8 |
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
7134X20
Com'l Only
7134X25
Com'l & Ind
7134X35
Com'l
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
t AS
t WP
t WR
t DW
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
20
15
15
0
15
0
15
____
____
____
____
____
____
____
25
20
20
0
20
0
15
____
____
____
____
____
____
____
35
30
30
0
25
0
20
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
15
____
15
____
20
ns
t DH
Data Hold Time
(3)
0
____
0
____
3
____
ns
t WZ
t OW
Write Enable to Output in High-Z (1,2)
Output Active from End-of-Write (1,2,3)
____
3
15
____
____
3
15
____
____
3
20
____
ns
ns
t WDD
Write Pulse to Data Delay
(4)
____
40
____
50
____
60
ns
t DDD
Write Data Valid to Read Data Delay
(4)
____
30
____
30
____
35
ns
2720 tbl 10a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
Write Enable to Output in High-Z
t WC
t EW
t AW
t AS
t WP
t WR
t DW
t HZ
t DH
t WZ
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1,2)
Data Hold Time (3)
(1,2)
45
40
40
0
40
0
20
____
3
____
____
____
____
____
____
____
____
20
____
20
55
50
50
0
50
0
25
____
3
____
____
____
____
____
____
____
____
25
____
25
70
60
60
0
60
0
30
____
3
____
____
____
____
____
____
____
____
30
____
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t OW
Output Active from End-of-Write
(1,2,3)
3
____
3
____
3
____
ns
t WDD
Write Pulse to Data Delay
(4)
____
70
____
80
____
90
ns
t DDD
Write Data Valid to Read Data Delay (4)
____
45
____
55
____
70
ns
NOTES:
2720 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage and
temperature, the actual t DH will always be smaller than the actual t OW .
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
8
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