参数资料
型号: IDT7140SA100C
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/21页
文件大小: 0K
描述: IC SRAM 8KBIT 100NS 48DIP
标准包装: 8
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 8K (1K x 8)
速度: 100ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 48-DIP(0.600",15.24mm)
供应商设备封装: 48-SIDE BRAZED
包装: 管件
其它名称: 7140SA100C
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
IDT7130SA/LA
IDT7140SA/LA
High-speed access
Low-power operation
Features
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
MASTER IDT7130 easily expands data bus width to 16-or-
Green parts available, see ordering information
more-bits using SLAVE IDT7140
Functional Block Diagram
OE L
CE L
R/ W L
OE R
CE R
R/ W R
I/O 0L - I/O 7L
I/O
Control
I/O
Control
I/O 0R -I/O 7R
,
BUSY R
BUSY L
(1,2)
(1,2)
A 9L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 9R
A 0R
10
10
CE L
OE L
R/ W L
ARBITRATION
and
INTERRUPT
LOGIC
CE R
OE R
R/ W R
INT R
NOTES:
INT L
(2)
2689 drw 01
(2)
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
?2013 Integrated Device Technology, Inc.
1
JANUARY 2013
DSC-2689/15
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