参数资料
型号: IDT71421LA25JI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/17页
文件大小: 0K
描述: IC SRAM 16KBIT 25NS 52PLCC
标准包装: 400
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 带卷 (TR)
其它名称: 71421LA25JI8
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/ W Controlled Timing) (1,5,8)
t WC
ADDRESS
t HZ (7)
OE
t AW
CE
t AS (6)
t WP (2)
t WR (3)
t HZ (7)
R/ W
t WZ (7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
DATA IN
2691 drw 08
Timing Waveform of Write Cycle No. 2, ( CE Controlled Timing) (1,5)
t WC
ADDRESS
t AW
CE
t WR
R/ W
t AS (6)
t EW (2)
t DW
(3)
t DH
DATA IN
2691 drw 09
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of CE = V IL and R/W= V IL .
3. t WR is measured from the earlier of CE or R/ W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be
placed on the bus for the required t DW . If OE is HIGH during a R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t WP .
10
6.42
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