参数资料
型号: IDT7142SA100C
厂商: IDT, Integrated Device Technology Inc
文件页数: 8/16页
文件大小: 0K
描述: IC SRAM 16KBIT 100NS 48DIP
标准包装: 8
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 16K (2K x 8)
速度: 100ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 48-DIP(0.600",15.24mm)
供应商设备封装: 48-SIDE BRAZED
包装: 管件
其它名称: 7142SA100C
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side (1)
t RC
ADDRESS
t OH
t AA
t OH
DATA OUT
BUSY OUT
PREVIOUS DATA VALID
t BDDH (2,3)
DATA VALID
2692 drw 07
Timing Waveform of Read Cycle No. 2, Either Side (1)
t ACE
CE
OE
DATA OUT
t AOE (3)
t LZ (4)
t HZ (5)
VALID DATA
t HZ (5)
t LZ
I CC
CURRENT
t PU
50%
(4)
t PD (3)
50%
I SS
2692 drw 08
NOTES:
1. R/ W = V IH, CE = V IL, and is OE = V IL. Address is valid prior to the coincidental with CE transition LOW.
2. t BDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA , and t BDD .
4. Timing depends on which signal is asserted last, OE or CE .
5. Timing depends on which signal is de-asserted first, OE or CE .
8
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