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参数资料
| 型号： | IDT7143LA25PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 25NS 100TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K（2K x 16） |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7143LA25PFI8 |
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (R/ W Controlled Timing) (1,5,8)
t WC
ADDRESS
OE
CE
t AS
(6)
t AW
t WR (3)
R/ W
(9)
t WP (2)
t HZ
(7)
DATA OUT
t LZ
(4)
t WZ (7)
t DW
t OW
t DH
(4)
t HZ (7)
DATA IN
2746 drw 09
Write Cycle No. 2 ( CE Controlled Timing) (1,5)
t WC
ADDRESS
t AW
CE
R/ W
(9)
t AS (6)
t EW (2)
t DW
t DH
t WR
DATA IN
2746 drw 10
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE = V IL and a R/ W = V IL .
3. t WR is measured from the earlier of CE or R/ W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
7. Timing depends on which enable signal is de-asserted first, CE or OE .
8. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t DW . If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t WP .
9. R/ W for either upper or lower byte.
11
6.42
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| IDT7143LA35FB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 35NS 68FPACK |
| IDT7143LA35G | 功能描述:IC SRAM 32KBIT 35NS 68PGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT7143LA35GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 35NS 68PGA |
| IDT7143LA35J | 功能描述:IC SRAM 32KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT7143LA35J8 | 功能描述:IC SRAM 32KBIT 35NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
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