参数资料
型号: IDT7143LA55PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/17页
文件大小: 0K
描述: IC SRAM 32KBIT 55NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 32K(2K x 16)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7143LA55PF8
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (1,2,3)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
t APS
DATA IN"A"
(1)
t DW
VALID
t DH
ADDR "B"
MATCH
t DDD
BUSY "B"
t WDD
DATA OUT "B"
NOTES:
1. To ensure that the earlier of the two ports wins, t APS is ignored for Slave (IDT7143).
2. CE L = CE R = V IL
3. OE = V IL for the reading port.
4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (3)
t WP
R/ W "A"
t WB
(4)
t BDA
t BDD
VALID
2746 drw 11
BUSY "B"
R/ W "B"
(2)
t WH
(1)
,
NOTES:
2746 drw 12
1. t WH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).
2. BUSY is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
3. All timing is the same for left and right ports. Port " A " may be either left or right port. Port " B " is the opposite from port " A ".
12
6.42
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