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参数资料
| 型号： | IDT7143SA90J |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 90 ns, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 3/16页 |
| 文件大小： | 140K |
| 代理商： | IDT7143SA90J |
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
!
"#!
NOTES:
1.
2.
3.
4.
5.
Both V
CC
pins must be connected to the power supply to ensure reliable operation.
Both GND pins must be connected to the ground supply to ensure reliable operation.
Package body is approximately 1.18 in x 1.18 in x 0.16 in.
This package code is used to reference the package diagram
This text does not indicate orientation of the actual part-marking.
2746drw 04
I/O
0L
V
CC(1)
A
10L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
51
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
I/O
15L
V
CC(1)
GND
(2
)
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
A
2L
A
1L
A
0L
R/
W
LUB
R/
W
LLB
OE
L
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
R/
W
RLB
R/
W
RUB
OE
R
GND
(2)
BUSY
L
BUSY
R
CE
L
CE
R
50
48
46
44
42
40
38
36
A
0R
A
1R
52
49
47
45
43
41
39
37
35
53
34
54
55
56
57
58
59
60
61
62
63
64
65
66
67
1
68
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
IDT7133/43G
GU68-1
(4)
68-Pin PGA
Top View
(5)
Pin 1
Designator
A
B
C
D
E
F
G
H
J
K
L
01
02
03
04
05
06
07
08
09
10
11
Left Port
Right Port
Names
CE
L
CE
R
Chip Enable
R/
W
LUB
R/
W
RUB
Upper Byte Read/Write Enable
R/
W
LLB
R/
W
RLB
Lower Byte Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
10L
A
0R
- A
10R
Address
I/O
0L
- I/O
15L
I/O
0R
- I/O
15R
Data Input/Output
BUSY
L
BUSY
R
Busy Flag
V
CC
Power
GND
Ground
2746 tbl 01
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