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参数资料
| 型号： | IDT7143SA90PFI |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS |
| 中文描述： | 高速2K × 16的CMOS双端口静态存储器 |
| 文件页数： | 8/16页 |
| 文件大小： | 140K |
| 代理商： | IDT7143SA90PFI |
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(5)
NOTES:
1. Timng depends on which signal is asserted last,
OE
or
CE
.
2. Timng depends on which signal is deasserted first,
OE
or
CE
.
3. t
BDD
delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations,
BUSY
has no
relationship to valid output data.
4. Start of valid data depends on which timng becomes effective last, t
AOE
, t
ACE
, t
AA,
or t
BDD
.
5. R/W = V
IH
, and the address is valid prior to or coincidental with
CE
transition LOW.
2746 drw 07
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
DATA VALID
PREVIOUS DATA VALID
BUSY
OUT
t
BDD
(3,4)
2746 drw 08
t
AOE
t
LZ
t
HZ
DATA
OUT
CE
t
ACE
VALID DATA
OE
CURRENT
I
CC
I
SB
t
PU
50%
t
LZ
t
PD
50%
t
HZ
(1)
(4)
(1)
(4)
(2)
(2)
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