- 您现在的位置：买卖IC网 > PDF目录20275 > IDT71T75902S85BGI8 (IDT, Integrated Device Technology Inc)IC SRAM 18MBIT 85NS 119BGA PDF资料下载
参数资料
| 型号： | IDT71T75902S85BGI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 85NS 119BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 18M（1M x 18） |
| 速度： | 85ns |
| 接口： | 并联 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 119-BGA |
| 供应商设备封装： | 119-PBGA（14x22） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71T75902S85BGI8 |
512K x 36, 1M x 18
2.5V Synchronous ZBT? SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
IDT71T75702
IDT71T75902
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 100 MHz
ZBT TM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
Single R/ W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write ( BW 1 - BW 4 ) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (V DDQ )
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
Features
x
x
(7.5 ns Clock-to-Data Access)
x
x
need to control OE
x
x
x
x
x
x
x
x
x
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT TM , or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
Pin Description Summary
The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable ( CEN ) pin allows operation of the IDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.
There are three chip enable pins ( CE 1 , CE 2 , CE 2 ) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/ LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/ LD signal is used to load a new
external address (ADV/ LD = LOW) or increment the internal burst counter
(ADV/ LD = HIGH).
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
A 0 -A 19
CE 1 , CE 2 , CE 2
OE
R/ W
CEN
BW 1 , BW 2 , BW 3 , BW 4
CLK
ADV/ LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
FEBRUARY 2004
APRIL 2009
5319 tbl 01
1
?2004 Integrated Device Technology, Inc.
DSC-5319/08
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71T75902S85BGI | IC SRAM 18MBIT 85NS 119BGA |
| VI-JNJ-CX-F2 | CONVERTER MOD DC/DC 36V 75W |
| IDT71T75902S85BGGI8 | IC SRAM 18MBIT 85NS 119BGA |
| VI-JNH-CX-F3 | CONVERTER MOD DC/DC 52V 75W |
| EEC05DRES-S734 | CONN EDGECARD 10POS .100 EYELET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71T75902S85PF | 功能描述:IC SRAM 18MBIT 85NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71T75902S85PF8 | 功能描述:IC SRAM 18MBIT 85NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71T75902S85PFI | 功能描述:IC SRAM 18MBIT 85NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71T75902S85PFI8 | 功能描述:IC SRAM 18MBIT 85NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71V016HSA12PH | 功能描述:IC SRAM 1MBIT 12NS 44TSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
发布紧急采购，3分钟左右您将得到回复。