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参数资料
| 型号： | IDT71V256SA20PZ |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 256KBIT 20NS 28TSOP |
| 产品变化通告： | Product Discontinuation 22/Jun/2009 |
| 标准包装： | 234 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 异步 |
| 存储容量： | 256K (32K x 8) |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 28-TSSOP（0.465"，11.8mm 宽） |
| 供应商设备封装： | 28-TSOP |
| 包装： | 管件 |
| 其它名称： | 71V256SA20PZ |
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 ( WE Controlled Timing) (1,2,4,6)
t WC
ADDRESS
OE
CS
t AW
t OHZ
(5)
WE
t AS
t WHZ (5)
t WP (6)
t WR
t OW (5)
DATA OUT
(3)
t DW
t DH
(3)
DATA IN
DATA VALID
3101 drw 09
,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE .
2. t WR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t WP or (t WHZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified t WP.
Timing Waveform of Write Cycle No. 2 ( CS Controlled Timing) (1,2,3,4)
t WC
ADDRESS
t AW
CS
t AS
t CW
(5)
t WR
WE
t DW
t DH
DATA IN
DATA VALID
3101 drw 10
,
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE .
3. t WR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t WP or (t WHZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified t WP.
6
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相关代理商/技术参数 |
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| IDT71V256SA20PZ8 | 功能描述:IC SRAM 256KBIT 20NS 28TSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 05/Nov/2008 标准包装:84 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 ZBT 存储容量:4.5M（128K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:119-BGA 供应商设备封装:119-PBGA（14x22） 包装:托盘 其它名称:71V3557SA75BGI |
| IDT71V256SA20PZG | 功能描述:IC SRAM 256KBIT 20NS 28TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V256SA20PZG8 | 功能描述:IC SRAM 256KBIT 20NS 28TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V256SA20PZGI | 功能描述:IC SRAM 256KBIT 20NS 28TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V256SA20PZGI8 | 功能描述:IC SRAM 256KBIT 20NS 28TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
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