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| 型号： | IDT71V3557SA80BGGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/28页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 4MBIT 80NS 119BGA |
| 产品变化通告： | Product Discontinuation 05/Nov/2008 |
| 标准包装： | 84 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 4.5M（128K x 36） |
| 速度： | 80ns |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 119-BGA |
| 供应商设备封装： | 119-PBGA（14x22） |
| 包装： | 托盘 |
| 其它名称： | 71V3557SA80BGGI |
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128K x 36, 256K x 18,
3.3V Synchronous ZBT? SRAMs
3.3V I/O, Burst Counter,
Flow-Through Outputs
IDT71V3557S
IDT71V3559S
IDT71V3557SA
IDT71V3559SA
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 100 MHz
Features
x
x
it read or write.
The IDT71V3557/59 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
x
x
x
x
x
x
x
x
x
(7.5 ns Clock-to-Data Access)
ZBT TM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates
the need to control OE
Single R/ W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write ( BW 1 - BW 4 ) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V (±5%) I/O Supply (V DDQ )
Optional Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
Packaged in a JEDEC Standard 100-pin plastic thin quad
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable ( CEN ) pin allows operation of the IDT71V3557/59
to be suspended as long as necessary. All synchronous inputs are
ignored when ( CEN ) is high and the internal device registers will hold
their previous values.
There are three chip enable pins ( CE 1 , CE 2 , CE 2 ) that allow the user
to deselect the device when desired. If any one of these three is not asserted
when ADV/ LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will
be completed. The data bus will tri-state one cycle after chip is de-
selected or a write is initiated.
The IDT71V3557/59 have an on-chip burst counter. In the burst
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array (fBGA)
Description
The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are
designed to eliminate dead bus cycles when turning the bus around
between reads and writes, or writes and reads. Thus they have been
given the name ZBT TM , or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
Pin Description Summary
mode, the IDT71V3557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/ LD signal is used to load a new
external address (ADV/ LD = LOW) or increment the internal burst counter
(ADV/ LD = HIGH).
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
A 0 -A 17
CE 1 , CE 2 , CE 2
OE
R/ W
CEN
BW 1 , BW 2 , BW 3 , BW 4
CLK
ADV/ LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5282 tbl 01
?2004 Integrated Device Technology, Inc.
1
DECEMBER 2005
DSC-5282/08
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V3557SA80BGGI8 | 功能描述:IC SRAM 4MBIT 80NS 119BGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V3557SA80BGI | 功能描述:IC SRAM 4MBIT 80NS 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V3557SA80BGI8 | 功能描述:IC SRAM 4MBIT 80NS 119BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V3557SA80BQ | 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V3557SA80BQ8 | 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
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