参数资料
型号: IDT71V3557SA80BQ
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/28页
文件大小: 0K
描述: IC SRAM 4MBIT 80NS 165FBGA
产品变化通告: Product Discontinuation 05/Nov/2008
标准包装: 136
格式 - 存储器: RAM
存储器类型: SRAM - 同步 ZBT
存储容量: 4.5M(128K x 36)
速度: 80ns
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-TBGA
供应商设备封装: 165-CABGA(13x15)
包装: 托盘
其它名称: 71V3557SA80BQ
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT? Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used (1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A 0
X
A 1
X
X
A 2
X
X
R/ W
X
X
H
X
H
X
X
H
X
X
ADV/ LD
L
L
L
L
L
L
L
L
L
L
CE 1 (2)
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
BW x
X
X
X
X
X
X
X
X
X
X
OE
X
X
X
L
X
L
X
X
L
X
I/O (3)
?
Z
Z
Q 0
Z
Q 1
Z
Z
Q 2
Z
Comments
Deselected.
Deselected.
Address A 0 and Control meet setup.
Address A 0 read out, Deselected.
Address A 1 and Control meet setup.
Address A 1 read out, Deselected.
Deselected.
Address A 2 and Control meet setup.
Address A 2 read out, Deselected.
Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used (1)
5282 tbl 19
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A 0
X
A 1
X
X
A 2
X
X
R/ W
X
X
L
X
L
X
X
L
X
X
ADV/ LD
L
L
L
L
L
L
L
L
L
L
CE (2)
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
BW x
X
X
L
X
L
X
X
L
X
X
OE
X
X
X
X
X
X
X
X
X
X
I/O
?
Z
Z
D 0
Z
D 1
Z
Z
D 2
Z
Comments
Deselected.
Deselected.
Address A 0 and Control meet setup
Data D 0 Write In, Deselected.
Address A 1 and Control meet setup
Data D 1 Write In, Deselected.
Deselected.
Address A 2 and Control meet setup
Data D 2 Write In, Deselected.
Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE 1 = L, CE 2 = L and CE2 = H. CE = H is defined as CE 1 = H, CE 2 = H or CE 2 = L.
14
6.42
5282 tbl 20
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