参数资料
型号: IDT71V3559SA75BQG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/28页
文件大小: 0K
描述: IC SRAM 4MBIT 75NS 165FBGA
产品变化通告: Product Discontinuation 05/Nov/2008
标准包装: 2,000
格式 - 存储器: RAM
存储器类型: SRAM - 同步 ZBT
存储容量: 4.5M(256K x 18)
速度: 75ns
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-TBGA
供应商设备封装: 165-CABGA(13x15)
包装: 带卷 (TR)
其它名称: 71V3559SA75BQG8
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT? Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation (1)
Cycle
n
n+1
Address
A 0
X
R/ W
H
X
ADV/ LD
L
X
CE 1 (2)
L
X
CEN
L
X
BW x
X
X
OE
X
L
I/O
X
Q 0
Comments
Address and Control meet setup
Contents of Address A 0 Read Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
Burst Read Operation (1)
5282 tbl 13
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A 0
X
X
X
X
A 1
X
A 2
R/ W
H
X
X
X
X
H
X
H
ADV/ LD
L
H
H
H
H
L
H
L
CE 1 (2)
L
X
X
X
X
L
X
L
CEN
L
L
L
L
L
L
L
L
BW x
X
X
X
X
X
X
X
X
OE
X
L
L
L
L
L
L
L
I/O
X
Q 0
Q 0+1
Q 0+2
Q 0+3
Q 0
Q 1
Q 1+1
Comments
Address and Control meet setup
Address A 0 Read Out, Inc. Count
Address A 0+1 Read Out, Inc. Count
Address A 0+2 Read Out, Inc. Count
Address A 0+3 Read Out, Load A 1
Address A 0 Read Out, Inc. Count
Address A 1 Read Out, Inc. Count
Address A 1+1 Read Out, Load A 2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
5282 tbl 14
Write Operation
(1)
Cycle
n
n+1
Address
A 0
X
R/ W
L
X
ADV/ LD
L
X
CE 1 (2)
L
X
CEN
L
L
BW x
L
X
OE
X
X
I/O
X
D 0
Comments
Address and Control meet setup
Write to Address A 0
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
5282 tbl 15
Burst Write Operation
(1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A 0
X
X
X
X
A 1
X
A 2
R/ W
L
X
X
X
X
L
X
L
ADV/ LD
L
H
H
H
H
L
H
L
CE 1 (2)
L
X
X
X
X
L
X
L
CEN
L
L
L
L
L
L
L
L
BW x
L
L
L
L
L
L
L
L
OE
X
X
X
X
X
X
X
X
I/O
X
D 0
D 0+1
D 0+2
D 0+3
D 0
D 1
D 1+1
Comments
Address and Control meet setup
Address A 0 Write, Inc. Count
Address A 0+1 Write, Inc. Count
Address A 0+2 Write, Inc. Count
Address A 0+3 Write, Load A 1
Address A 0 Write, Inc. Count
Address A 1 Write, Inc. Count
Address A 1+1 Write, Load A 2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
12
6.42
5282 tbl 16
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