参数资料
型号: IDT71V35761S183BQ
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/21页
文件大小: 0K
描述: IC SRAM 4MBIT 183MHZ 165FBGA
产品变化通告: Product Discontinuation 05/Nov/2008
标准包装: 136
格式 - 存储器: RAM
存储器类型: SRAM - 同步
存储容量: 4.5M(128K x 36)
速度: 183MHz
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-TBGA
供应商设备封装: 165-CABGA(13x15)
包装: 托盘
其它名称: 71V35761S183BQ
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Synchronous Write Function Truth Table (1)
Commercial and Industrial Temperature Ranges
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Operation
Read
Read
Write all Bytes
Write all Bytes
(3)
(3)
(3)
(3)
GW
H
H
L
H
H
H
H
H
BWE
H
L
X
L
L
L
L
L
BW 1
X
H
X
L
L
H
H
H
BW 2
X
H
X
L
H
L
H
H
BW 3
X
H
X
L
H
H
L
H
BW 4
X
H
X
L
H
H
H
L
NOTES:
1. L = V IL , H = V IH , X = Don’t Care.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table (1)
5301 tbl 12
Operation (2)
Read
Read
Write
Deselected
Sleep Mode
OE
L
H
X
X
X
ZZ
L
L
L
L
H
I/O Status
Data Out
High-Z
High-Z – Data In
High-Z
High-Z
Power
Active
Active
Active
Standby
Sleep
NOTES:
1. L = V IL , H = V IH , X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO =V DD )
5301 tbl 13
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
Second Address
Third Address
0
0
1
0
1
0
0
0
1
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
Fourth Address
(1)
1
1
1
0
0
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO =V SS )
5301 tbl 14
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
Second Address
Third Address
Fourth Address (1)
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
10
6.42
5301 tbl 15
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