- 您现在的位置：买卖IC网 > PDF目录4175 > IDT71V3577S80PFG (IDT, Integrated Device Technology Inc)IC SRAM 4MBIT 80NS 100TQFP PDF资料下载
参数资料
| 型号： | IDT71V3577S80PFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/22页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 4MBIT 80NS 100TQFP |
| 标准包装： | 72 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 |
| 存储容量： | 4.5M（128K x 36） |
| 速度： | 80ns |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 71V3577S80PFG |
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V3577S
IDT71V3579S
IDT71V3577SA
IDT71V3579SA
128K x 36, 256K x 18 memory configurations
Features
◆
Description
The IDT71V3577/79 are high-speed SRAMs organized as
◆
◆
◆
◆
◆
◆
◆
◆
Supports fast access times:
Commercial:
– 6.5ns up to 133MHz clock frequency (TQFP package only)
Commercial and Industrial:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control ( GW ), byte write
enable ( BWE ), and byte writes ( BW x)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected ( ADV =LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A 0 -A 17
CE
CS 0 , CS 1
OE
GW
BWE
BW 1 , BW 2 , BW 3 , BW 4 (1)
CLK
ADV
ADSC
ADSP
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
NOTE:
1. BW 3 and BW 4 are not applicable for the IDT71V3579.
?2012 Integrated Device Technology, Inc.
1
6450tbl 01
APRIL 2012
DSC-6450/1
相关PDF资料 |
PDF描述 |
|---|---|
| AMM28DSAI | CONN EDGECARD 56POS R/A .156 SLD |
| AMM10DREN | CONN EDGECARD 20POS .156 EYELET |
| ABB60DHBS-S621 | CONN EDGECARD 120PS R/A .050 SLD |
| ABB60DHBS | CONN EDGECARD 120PS R/A .050 SLD |
| ACB60DHBS-S621 | EDGECARD 120POS DIP R/A .050 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V3577S80PFG8 | 功能描述:IC SRAM 4MBIT 80NS 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V3577S80PFGI | 功能描述:IC SRAM 4MBIT 80NS 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:MoBL® 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并联 电源电压:2.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-VFBGA 供应商设备封装:48-VFBGA（6x8） 包装:带卷 (TR) |
| IDT71V3577S80PFGI8 | 功能描述:IC SRAM 4MBIT 80NS 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| IDT71V3577S80PFI | 功能描述:IC SRAM 4MBIT 80NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
| IDT71V3577S80PFI8 | 功能描述:IC SRAM 4MBIT 80NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
发布紧急采购，3分钟左右您将得到回复。