参数资料
型号: IDT71V424YS12PH
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/9页
文件大小: 0K
描述: IC SRAM 4MBIT 12NS 44TSOP
产品变化通告: Product Discontinuation 29/Apr/2010
标准包装: 26
格式 - 存储器: RAM
存储器类型: SRAM - 异步
存储容量: 4M (512K x 8)
速度: 12ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 44-TSOP(0.400",10.16mm 宽)
供应商设备封装: 44-TSOP II
包装: 管件
其它名称: 71V424YS12PH
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 ( WE Controlled Timing) (1, 2, 4)
t WC
ADDRESS
t AW
CS
t WR
WE
t AS
t WP
(2)
DATA OUT
(3)
t WHZ
(5)
HIGH IMPEDANCE
t OW
(5)
(3)
t CHZ (5)
t DW
t DH
DATA IN
DATA IN VALID
3622 drw 08
Timing Waveform of Write Cycle No. 2 ( CS Controlled Timing) (1, 4)
t WC
ADDRESS
t AW
CS
WE
DATA IN
t AS
t CW
t WR
t DW
DATA IN VALID
t DH
3622 drw 09
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE .
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t WP must be greater than or equal to t WHZ + t DW to allow the I/O drivers to turn off and
data to be placed on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified t WP .
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the t CW
write period.
5. Transition is measured ±200mV from steady state.
7
6.42
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