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参数资料
| 型号： | IDT71V65603S150PFGI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 9MBIT 150MHZ 100TQFP |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 9M（256K x 36） |
| 速度： | 150MHz |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71V65603S150PFGI8 |
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT ? Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definitions (1)
Symbol
A 0 -A 18
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/ LD low, CEN low, and true chip enables.
ADV/ LD
Advance / Load
I
N/A
ADV/ LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/ LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD
is sampled hig h then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/ LD is sampled high.
R/ W
Read / Write
I
N/A
R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs re main unchanged. The effect of CEN
sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
BW 1 - BW 4
Individual Byte
Write Enables
I
LOW
Synchro nous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/ W and ADV/ LD are sampled low) the appropriate byte write
signal ( BW 1 - BW 4 ) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/ W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW 1 - BW 4 can all be tied low if
always doing write to the entire 36-bit word.
CE 1 , CE 2
Chip Enables
I
LOW
Synchronous active low chip enable. CE 1 and CE 2 are used with CE 2 to enable the
IDT71V65603/5803. ( CE 1 or CE 2 sampled high or CE 2 sampled low) and ADV/ LD low at the
rising edge of clock, initiates a deselect cycle. The ZBT TM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE 2
Chip Enable
I
HIGH
Synchrono us active high chip enable. CE 2 is used with CE 1 and CE 2 to enable the chip.
CE 2 has inverted po larity but otherwise identical to CE 1 and CE 2 .
CLK
Clock
I
N/A
This is the clock input to the IDT71V65603/5803. Except for OE , all timing references for the
device are made with respect to the rising edge of CLK.
I/O 0 -I/O 31
Data Input/Output
I/O
N/A
Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
I/O P1 -I/O P4
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Line ar burst sequence is selected. LBO is a static input and it must
not change during device operation.
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V65603/5803. When
OE is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In normal operation, OE can be tied low.
ZZ
Sleep Mode
I
N/A
Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
71V65603/5803 to its lowest p ower consumption level. Data retention is guaranteed in
Sleep Mode.
V DD
V DDQ
V SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
5304tbl 02
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