- 您现在的位置：买卖IC网 > PDF目录4100 > IDT71V65703S75BG8 (IDT, Integrated Device Technology Inc)IC SRAM 9MBIT 75NS 119BGA PDF资料下载
参数资料
| 型号： | IDT71V65703S75BG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/26页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 9MBIT 75NS 119BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 9M（256K x 36） |
| 速度： | 75ns |
| 接口： | 并联 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 119-BGA |
| 供应商设备封装： | 119-PBGA（14x22） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71V65703S75BG8 |
256K x 36, 512K x 18
3.3V Synchronous ZBT? SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
IDT71V65703
IDT71V65903
256K x 36, 512K x 18 memory configurations
Features
x
cycle, and on the next clock cycle the associated data cycle occurs, be it
read or write.
x
x
x
x
x
x
x
x
x
x
x
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT TM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/ W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write ( BW 1 - BW 4 ) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V (±5%) I/O Supply (V DDQ )
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
The IDT71V65703/5903 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable ( CEN ) pin allows operation of the IDT71V65703/5903
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
CEN is high and the internal device registers will hold their previous values.
There are three chip enable pins ( CE 1 , CE 2 , CE 2 ) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/ LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71V65703/5903 have an on-chip burst counter. In the burst
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT TM , or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
Pin Description Summary
mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/ LD signal is used to load a new
external address (ADV/ LD = LOW) or increment the internal burst counter
(ADV/ LD = HIGH).
The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
A 0 -A 18
CE 1 , CE 2 , CE 2
OE
R/ W
CEN
BW 1 , BW 2 , BW 3 , BW 4
CLK
ADV/ LD
LBO
ZZ
I/O 0 -I/O 31 , I/O P1 -I/O P4
V DD , V DDQ
V SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5298 tbl 01
DECEMBER 2002
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
1
?2002 Integrated Device Technology, Inc.
MARCH 2009
DSC-5298/03
相关PDF资料 |
PDF描述 |
|---|---|
| MPC860ENVR80D4 | IC MPU POWERQUICC 80MHZ 357PBGA |
| IDT71V65603S150BGG8 | IC SRAM 9MBIT 150MHZ 119BGA |
| 1-84952-9 | CONN FPC 19POS 1MM RT ANG SMD |
| IDT71V65603S150BG8 | IC SRAM 9MBIT 150MHZ 119BGA |
| IDT71V65603S133BGG8 | IC SRAM 9MBIT 133MHZ 119BGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT71V65703S75BGG | 功能描述:IC SRAM 9MBIT 75NS 119BGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT71V65703S75BGG8 | 功能描述:IC SRAM 9MBIT 75NS 119BGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65703S75BQ | 功能描述:IC SRAM 9MBIT 75NS 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65703S75BQ8 | 功能描述:IC SRAM 9MBIT 75NS 165FBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT71V65703S75BQG | 功能描述:IC SRAM 9MBIT 75NS 165FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
发布紧急采购，3分钟左右您将得到回复。