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| 型号： | IDT72255LA15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 21/27页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 8KX18 LP 15NS 64QFP |
| 标准包装： | 90 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 144K（8K x 18） |
| 访问时间： | 15ns |
| 电源电压： | 4 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 72255LA15PF |
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3
IDT72255LA/72265LA CMOS SuperSync FIFO
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72255LA
72265LA
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (RT)
4670 drw03
HALF FULL FLAG (HF)
SERIAL ENABLE(SEN)
In FWFT mode, the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of the RCLK signal. A
RENdoesnot
have to be asserted for accessing the first word. However, subsequent words
writtentotheFIFOdorequireaLOWon
RENforaccess. ThestateoftheFWFT/
SI input during Master Reset determines the timing mode in use.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR(EmptyFlagorOutputReady),FF/
IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost-
Emptyflag)and
PAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions
are selected in IDT Standard mode. The
IRand OR functions are selected in
FWFT mode.
HF, PAE and PAF are always available for use, irrespective of
timingmode.
PAE and PAF can be programmed independently to switch at any point in
memory. (See Table I and Table 2.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that
PAEcanbesettoswitchat127
or 1,023 locations from the empty boundary and the
PAFthresholdcanbeset
at 127 or 1,023 locations from the full boundary. These choices are made with
the
LD pin during Master Reset.
For serialprogramming,
SENtogetherwithLDoneachrisingedgeofWCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WENtogetherwithLDoneachrisingedgeofWCLK,areused
to load the offset registers via Dn.
REN together with LD on each rising edge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serial or parallel offset loading has been selected.
During Master Reset (
MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
with serial programming. The flags are updated according to the timing mode
anddefaultoffsetsselected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag programming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.
PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RTinputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72255LA/72265LA are fabricated using IDT’s high speed submi-
cron CMOS technology.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72255LA15PF8 | 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72255LA15PFG | 功能描述:IC FIFO SUPERSYNC 8KX18 64QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72255LA15PFGI | 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72255LA15PFGI8 | 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72255LA15PFI | 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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