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参数资料
| 型号： | IDT723631L20PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 19/21页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 512X36 120-TQFP |
| 标准包装： | 45 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 18.4K（512 x 36） |
| 数据速率： | 50MHz |
| 访问时间： | 20ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 723631L20PF |
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1,024 x 36 and 2,048 x 36
7
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ± 10%, TA = 0
°C to +70°C; Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l(1)
IDT723631L15
IDT723631L20
IDT723641L15
IDT723641L20
IDT723651L15
IDT723651L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
15
–
20
–
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
6
–
8
–
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
6
–
8
–
ns
tDS
Setup Time, A0-A35 before CLKA
↑and B0-B35 before CLKB↑
5
–6–
ns
tENS1
Setup Time, ENA to CLKA
↑; ENB to CLKB↑
5
–6–
ns
tENS2
Setup Time,
CSA, W/RA, and MBA to CLKA
↑; CSB, W/RB and MBB to CLKB↑
7
–
7.5
–
ns
tRMS
Setup Time, RTM and RFM to CLKB
↑
6
–
6.5
–
ns
tRSTS
Setup Time,
RST LOW before CLKA
↑ or CLKB↑(2)
5
–6–
ns
tFSS
Setup Time, FS0 and FS1 before
RST HIGH
9
–
10
–
ns
tSDS(3)
Setup Time, FS0/SD before CLKA
↑
5
–6–
ns
tSENS(3)
Setup Time, FS1/
SEN before CLKA
↑
5
–6–
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35 after CLKB↑
0
–0–
ns
tENH1
Hold Time, ENA after CLKA
↑; ENB after CLKB↑
0
–0–
ns
tENH2
Hold Time,
CSA, W/RA, and MBA after CLKA
↑; CSB, W/RB and MBB after CLKB↑
0
–0–
ns
tRMH
Hold Time, RTM and RFM after CLKB
↑
0
–0–
ns
tRSTH
Hold Time,
RST LOW after CLKA
↑ or CLKB↑(2)
5
–6–
ns
tFSH
Hold Time, FS0 and FS1 after
RST HIGH
0
–
0
–
ns
tSPH(3)
Hold Time, FS1/
SEN HIGH after RST HIGH
0
–
0
–
ns
tSDH(3)
Hold Time, FS0/SD after CLKA
↑
0
–0–
ns
tSENH(3)
Hold Time, FS1/
SEN after CLKA
↑
0
–0–
ns
tSKEW1(4)
Skew Time, between CLKA
↑ and CLKB↑ for OR and IR
9
–
11
–
ns
tSKEW2(4)
Skew Time, between CLKA
↑and CLKB↑ for AE and AF
12
–
16
–
ns
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Only applies when serial load method is used to program flag Offset registers.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
5. Design simulated but not tested (typical values).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT723631L20PF8 | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723631L20PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 512X36 120-TQFP |
| IDT723631L20PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 512X36 120-TQFP |
| IDT723631L20PFI | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT723631L20PFI8 | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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