- 您现在的位置：买卖IC网 > PDF目录2076 > IDT723644L12PF (IDT, Integrated Device Technology Inc)IC FIFO SYNC 2048X36 128QFP PDF资料下载
参数资料
| 型号： | IDT723644L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/35页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 2048X36 128QFP |
| 标准包装： | 72 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 72K（2K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723644L12PF |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
3
COMMERCIALTEMPERATURERANGE
IDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Communication between each port may bypass the FIFOs via two
mailboxregisters.ThemailboxregisterwidthmatchestheselectedPortBbus
width. Each Mailbox register has a flag (
MBF1andMBF2)tosignalwhennew
mail has been stored.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array, configures the FIFO for Big- or Little-Endian byte
arrangement and selects serial flag programming, parallel flag programming,
or one of three possible default flag offset settings, 8, 16 or 64. There are two
Master Reset pins,
MRS1 and MRS2.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word(36-bitwide)writtentoanemptyFIFOappearsautomaticallyonthe
outputs, no read operation is required (nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFTpin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).
The
EFandFFfunctionsareselectedintheIDTStandardmode.EFindicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEAandAEB)and
aprogrammableAlmost-Fullflag(
AFAandAFB). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFBindicate
when the FIFO contains more than a selected number of words.
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport
clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA and AEB are
two-stage synchronized to the port clock that reads data from its array.
Programmableoffsetsfor
AEA,AEB,AFAandAFBareloaded inparallelusing
Port A or in serial via the SD input. The Serial Programming Mode pin (
SPM)
makes this selection. Three default offset settings are also provided. The
AEA
and
AEBthresholdcanbesetat8,16or64locationsfromtheemptyboundary
and the
AFAandAFBthresholdcanbesetat8,16or64locationsfromthefull
boundary. All these choices are made using the FS0 and FS1 inputs during
Master Reset.
Two or more devices may be used in parallel to create wider data
paths. If, at any time, the FIFO is not actively performing a function, the chip
will automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating
control inputs) will immediately take the device out of the power down state.
The IDT723624/723634/723644 are characterized for operation from
0°C to 70°C. Industrial temperature range (-40
°Cto+85°C)isavailable.They
are fabricated using IDT’s high speed, submicron CMOS technology.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT723646L12PF | IC FIFO SYNC 2048X36 128QFP |
| IDT723651L20PQFI | IC FIFO SYNC 2048X36 132QFP |
| IDT723653L15PF8 | IC FIFO SYNC 2048X36 128-TQFP |
| IDT723672L12PQF | IC FIFO SYNC 16384X36 132QFP |
| IDT723676L12PF | IC FIFO SYNC 16384X36 128QFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT723644L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723644L15PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723644L15PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L12PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723646L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
发布紧急采购，3分钟左右您将得到回复。