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参数资料
| 型号： | IDT723656L15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/39页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 4096X36 128QFP |
| 标准包装： | 36 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 147K（4K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723656L15PF |
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11
COMMERCIALTEMPERATURERANGE
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2 )
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723656/723666/723676 undergoes a complete reset by
takingitsassociatedMasterReset(
MRS1)inputLOWforatleastfourPortAClock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(
MRS2)inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
writepointerstothefirstlocationofthememoryandforcestheFull/InputReady
flag(
FFA/IRA,FFC/IRC)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/
ORB) LOW, the Almost-Empty flag (
AEA,AEB)LOWandtheAlmost-Fullflag
(
AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(
MBF1,MBF2)oftheparallelmailboxregisterHIGH. AfteraMasterReset,the
FIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles. Thenthe
FIFO is ready to be written to.
ALOW-to-HIGHtransitionontheFIFO1MasterReset(
MRS1)inputlatches
the value of the Big-Endian (BE) input for determining the order by which bytes
aretransferredthroughPortsBandC. ItalsolatchesthevaluesoftheFlagSelect
(FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost-Empty
offsetsandprogrammingmethod.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(
MRS2)clearstheflag
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2
Master Reset (
MRS2) together with the FIFO1 Master Reset input (MRS1)
latchesthevalueoftheBig-Endian(BE)inputforPortsBandCandalsolatches
thevaluesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetsandprogrammingmethod(fordetailsseeTable
1, Flag Programming, and Almost-Empty and Almost-Full flag offset program-
ming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.
Note that MBC must be HIGH during Master Reset (until
FFA/IRA and
FFC/IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master
Reset.
PARTIAL RESET (
PRS1, PRS2)
The FIFO1 memory of these devices undergoes a limited reset by taking its
associatedPartialReset(
PRS1)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2 memory
undergoes a limited reset by taking its associated Partial Reset (
PRS2)input
LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC) LOW-
to-HIGHtransitions.TheRTMpinmustbeLOWduringthetimeofpartialreset.
ThePartialResetinputscanswitchasynchronouslytotheclocks. APartialReset
initializes the internal read and write pointers and forces the Full/Input Ready
flag(
FFA/IRA,FFC/IRC)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/
ORB) LOW, the Almost-Empty flag (
AEA,AEB)LOW,andtheAlmost-Fullflag
(
AFA,AFC)HIGH. APartialResetalsoforcestheMailboxFlag(MBF1,MBF2)
oftheparallelmailboxregisterHIGH. AfteraPartialReset,theFIFO’sFull/Input
Ready flag is set HIGH after two Write Clock cycles.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation. APartialResetmaybeusefulinthecasewherereprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
RETRANSMIT (
RT1, RT2 )
The FIFO1 memory of these devices undergoes a Retransmit by taking its
associated Retransmit (
RT1)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit(
RT2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
CClock(CLKC)LOW-to-HIGHtransitions. TheRetransmitinitializestheread
pointer of FIFO1 to the first memory location.
TheRTMpinmustbeHIGHduringthetimeofRetransmit. Notethatthe
RT1
inputismuxedwiththePRS1input,thestateoftheRTMpindeterminingwhether
this pin performs a Retransmit or Partial Reset. Also, the
RT2inputismuxed
with the
PRS2 input, the state of the RTM pin determining whether this pin
performs a Retransmit or Partial Reset. See Figures 30, 31, 32 and 33 for
Retransmittimingdiagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH ( BE/
FWFT )
— ENDIAN SELECTION
Thisisadualpurposepin. AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big- or Little-Endian byte arrangement for data
written to Port C or read from Port B. This selection determines the order by
which bytes (or words) of data are transferred through those ports. For the
followingillustrations,notethatbothportsB andCareconfiguredtohaveabyte
(or a word) bus size.
AHIGHontheBE/
FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; the least significant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast. When
data is moving in the direction from Port C to Port A, the byte (word) written to
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
ALOWontheBE/
FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast. When
data is moving in the direction from Port C to Port A, the byte (word) written to
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
— TIMING MODE SELECTION
AfterMasterReset,theFWFTselectfunctionisavailable,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through(FWFT)mode. OncetheMasterReset(
MRS1, MRS2)inputisHIGH,
aHIGHontheBE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(for FIFO1) and CLKC (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (
EFA,EFB)toindicatewhetherornotthereare
any words present in the FIFO memory. It uses the Full Flag function (
FFA,
FFC)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
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相关代理商/技术参数 |
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| IDT723656L15PF8 | 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L12PF | 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L12PF8 | 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L12PQF | 功能描述:IC FIFO BI SYNC 8192X36 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L15PF | 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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