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参数资料
| 型号： | IDT723662L12PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | IC FIFO BI SYNC 8192X36 120QFP |
| 标准包装： | 45 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 288K（8K x 36） |
| 数据速率： | 83MHz |
| 访问时间： | 12ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 723662L12PF |
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13
COMMERCIALTEMPERATURERANGE
IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
ALMOST-FULL FLAGS (
AFA, AFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwritesdata
toitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsawrite
pointer and read pointer comparator that indicates when the FIFO memory
statusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstateisdefined
by the contents of register Y1 for
AFAandregisterY2forAFB. Theseregisters
are loaded with preset values during a FlFO reset or programmed from port
A (see Almost-Empty flag and Almost-Full flag offset programming section).
AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT723652, IDT723662,
or IDT723672 respectively. An Almost-Full flag is HIGH when the number of
wordsinitsFIFOislessthanorequalto[2,048-(Y+1)],[4,096-(Y+1)],or[8,192-
(Y+1)] for the IDT723652, IDT723662, or IDT723672 respectively. Note that
a data word present in the FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [2,048/
4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-
HIGH transition of its synchronizing clock after the FIFO read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchroni-
zation cycle if it occurs at time tSKEW2or greater after the read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figures 18 and 19).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The Mailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation. ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
to the mail1 register when a port A Write is selected by
CSA, W/RA, and ENA
and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data
to the mail2 register when a port B Write is selected by
CSB, W/RB, and ENB
and with MBB HIGH. Writing data to a mail register sets its corresponding flag
(
MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while
the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthemail
register when the port mailbox select input is HIGH. The Mail1 Register Flag
(
MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhenaportBRead
is selected by
CSB,W/RB,andENBandwithMBBHIGH. TheMail2Register
Flag (
MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port
A read is selected by
CSA, W/RA, and ENA and with MBA HIGH. The data
in a mail register remains intact after it is read and changes only when new data
iswrittentotheregister. FormailregisterandMailRegisterFlagtimingdiagrams,
see Figure 20 and 21.
can be the first synchronization cycle (see Figures 8 through 11 for
EFA/ORA
and
EFB/ORBtimingdiagrams).
FULL/INPUT READY FLAGS (
FFA/IRA, FFB/IRB)
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB)
function is selected. In IDT Standard mode, the Full Flag (
FFA and FFB)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 12 through 15 for
FFA/IRA
and
FFB/IRBtimingdiagrams).
ALMOST-EMPTY FLAGS (
AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
datafromitsarray. ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1for
AEBandregister
X2 for
AEA. TheseregistersareloadedwithpresetvaluesduringaFIFOreset
or programmed from port A (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Empty flag is LOW when its FIFO contains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level. AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figures 16 and 17).
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| IDT723662L12PF8 | 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L12PQF | 功能描述:IC FIFO BI SYNC 8192X36 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L15PF | 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L15PF8 | 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723662L15PQF | 功能描述:IC FIFO BI SYNC 8192X36 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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